Cadence announced a Chiplet Spec-to-Packaged Parts ecosystem aimed at simplifying development for customers building chiplets for physical AI, data center, and high-performance computing applications. Initial IP partners include Arm, Arteris, eMemory, M31 Technology, Silicon Creations, and Trilinear Technologies, with proteanTecs as the silicon analytics partner. Cadence is also working with Samsung Foundry on a silicon prototype demonstration of the Cadence Physical AI chiplet platform, using pre-integrated partner IP on Samsung Foundry’s SF5A process.
Building on their existing collaboration, Cadence and Arm are working together on physical and infrastructure AI applications. Cadence plans to use the Arm Zena Compute Subsystem (CSS) and other IP to expand its Physical AI chiplet platform and Chiplet Framework. The resulting Cadence solutions are intended to support edge AI processing for automobiles, robotics and drones, along with standards-based I/O and memory chiplets for data center, cloud and HPC applications. The companies say the work aims to reduce engineering complexity and help customers adopt chiplets with lower implementation risk.
Cadence has developed spec-driven automation to generate chiplet framework architectures that integrate Cadence IP and third-party partner IP, along with chiplet management, security, and safety functions supported by software. The generated EDA flow supports simulation with the Cadence Xcelium Logic Simulator and emulation with the Cadence Palladium Z3 Enterprise Emulation Platform. The physical design flow uses real-time feedback to support iterative place-and-route cycles. The resulting chiplet architectures are designed to align with relevant standards for interoperability, including the Arm Chiplet System Architecture and the planned OCP Foundational Chiplet System Architecture.
Cadence’s Universal Chiplet Interconnect Express (UCIe) IP provides die-to-die connectivity, and its protocol IP portfolio supports integration of interfaces such as LPDDR6/5X, DDR5-MRDIMM, PCI Express (PCIe) 7.0, and HBM4.
An earlier prototype of the Cadence base system chiplet, part of the Cadence Physical AI chiplet platform, incorporates the Cadence chiplet framework, UCIe 32G, and LPDDR5X IP and has been silicon validated.
For more information, visit cadence.com.
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